This invention relates to a method and apparatus to decode a specific received address input with a minimum of semiconductor area being utilized, using only noncomplementary address inputs.
Heretofore, both the true and complement of the address inputs were coupled to the memory address decode, and the address was decoded with either a programmable logic array (PLA) or with a static gate array. A key disadvantage of this technique is that both the true and complement address input signals are required for the decoder to properly operate. Thus, either inverters must be provided to couple to non-complementary inputs to provide a set of complementary inputs, which increases the bar size area of the semiconductor needed for the decode array, or both true and complementary address lines must be provided for, which increases the layout complexity and bar size of the overall integrated circuit upon which the decode array is to be located. Therefore, to minimize the number of interconnect lines and bar area required for the address decode, it is necessary to provide for decode without the use of complementary address inputs.